Aspects are related generally to computer-based communication systems, and more specifically to simultaneous inbound multi-packet processing in a computer system.
Peripheral component interconnect express (PCIe) is a component level interconnect standard that defines a bi-directional communication protocol for transactions between input/output (I/O) adapters and host systems. PCIe communications are encapsulated in packets according to the PCIe standard for transmission on a PCIe bus. Packets originating at I/O adapters and ending at host systems are referred to as upbound packets. Packets originating at host systems and terminating at I/O adapters are referred to as downbound packets. PCIe transactions include a request packet and, if required, a completion packet (also referred to herein as a “response packet”) in the opposite direction. The PCIe topology is based on point-to-point unidirectional links that are paired (e.g., one upbound link, one downbound link) to form the PCIe bus.
A high-bandwidth PCIe link (×16) can transmit two full transaction layer packets (TLPs) in a single scaled clock cycle and must process two pipelines and two TLPs in a single cycle. Two TLPs can be received in a single cycle, so the path is broken into two separate processing pipelines. Each pipeline has a separate header (16 byte wide) and data (32 byte wide) path. Both pipelines feed the same arrays (shared arrays) with a 32 byte wide data path. There is a need for a way to write two of the same TLP type (e.g., posted/non-posted/completion), 32 bytes per cycle, into the same array. There is also a need to be able to read this data out in the order it was received off the link sequentially. PCIe variations can add further complications, for instance, PCIe flow control is managed in 16 byte increments, not 32 byte increments.